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Automating makefile for all files in a certain directory

I have a folder (./tests/) that contains a bunch of c files, a.c, b.c, d.c, ..., y.z, z.c. They all contain a main function. I want to write a Makefile that will compile all of the files in that directory independently. Something like this:

test_a: ./tests/a.c $(STUFF)
    gcc $< $(STUFF) $(OTHERSTUFF)

test_b: ./tests/b.c $(STUFF)
    gcc $< $(STUFF) $(OTHERSTUFF)

test_c: ./tests/c.c $(STUFF)
    gcc $< $(STUFF) $(OTHERSTUFF)

test_d: ./tests/d.c $(STUFF)
    gcc $< $(STUFF) $(OTHERSTUFF)

...


test_z: ./tests/z.c $(STUFF)
    gcc $< $(STUFF) $(OTHERSTUFF)

The only difference between all of these targets is the letter in the target name (test_X), and the letter in the first prerequisite (./tests/X.c), which is the same X. So, how could I automate this process so that I dont need to copy and paste the same target a bunch of times?


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Assuming you have GNU make, it's pretty simple:

SRCS := $(wildcard tests/*.c)
TARGETS := $(notdir $(SRCS:.c=))

all: $(TARGETS)

$(TARGETS): $(STUFF)

test_%: tests/%.c
        $(CC) -o [email protected] $^ $(OTHERSTUFF)

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